International Journal of Research and Innovations in Science and Technology (Dec 2015)
High Speed Linear Pipeline Multiplier for Signed-Unsigned Number Operating at 20 GHz
Abstract
In this paper we proposed an 8 × 8 synchronous pipeline multiplier for signed-unsigned number operating at 20 GHz. This multiplier is designed using three stage pipelined operation. During first stage of the pipelined operation all the 53 bits of the partial products are generated by the Multiplexer based Modified Booth Encoder (MMBE) technique and lathed into the 53 bit register. During second stage of the pipelined operation, the five partial products are reduced to the array of only two rows by using VCA as the PPRT and are latched into the 32 bit register. During third stage of pipeline operation the final product is obtained by using the CLCSA as the CPA and latched into the 16 bit register. The pipe stage fills up in three clock cycles, and once the pipeline is filled up, then every clock cycle the new product of 8-bit signed unsigned number is obtained. The delay measured of MMBE is 0.023 ns, VCA is 0.036 ns and CLCSA is 0.050 ns. Since the maximum delay of the pipeline stage has been used as the clock signal, therefore the delay of CLCSA stage has been used as the pipeline clock signal and hence each pipeline stage is operated with frequency of 20 GHz. Experimental results has been obtained using the 45 nm CMOS technology for 8 × 8 pipelined multiplier. The delay, area and power consumption has been measured. Comparison of results shows that our proposed three stage pipeline multiplier has been improved in delay by 26 %, area reduced by 53 % and power dissipation saved by 54 %.
