Quasi delay insensitive implementation of approximate multiplication

Abstract

Asynchronous quasi delay insensitive (QDI) implementation of approximate multiplication is described in this article. We consider the array multiplier architecture for a QDI implementation. We obtain approximate QDI array multipliers by introducing vertical cuts in an accurate QDI array multiplier and then assign different combinations of binary values to the dangling internal inputs and some less significant product bits whose logic were eliminated. The usefulness of the proposed approximate array multipliers is analyzed through an image denoising application. One of the approximate array multiplier architectures consistently yields denoised images which closely resembles the denoised images obtained using the accurate array multiplier. Also, it achieves 32.6% reduction in cycle time, 64.2% reduction in area and 26.3% reduction in power on average compared to the optimum accurate QDI array multiplier when considering both return-to-zero and return-to-one handshaking. The accurate and approximate QDI array multipliers were realized using a 32/28-nm CMOS technology.

Keywords

• Approximate computing
• Asynchronous circuits
• Arithmetic circuits
• Digital circuits
• Low power
• High speed