A True Random Number Generator Based on Race Hazard and Jitter of Braided and Cross-Coupled Logic Gates Using FPGA

Abstract

In the contemporary digital landscape, security has become a vital element of our existence. The growing volume of sensitive information being stored and transmitted over networks necessitates the implementation of robust security measures. Cryptographic algorithms, which are critical for protecting user data privacy, rely on cryptographic keys to ensure data security. True Random Number Generators (TRNGs) are essential to numerous vital security applications. In this paper, we propose a novel Braided and Hybrid Cross-Coupled Entropy Source (B+HCCES) TRNG module. The proposed B+HCCES TRNG module generates random numbers based on the race hazard and jitter of braided and cross-coupled combinational logic gates. The B+HCCES architecture has been designed using VHDL, and the targeted Field-Programmable Gate Array (FPGA) is the Intel Cyclone V 5CGXFC9D6F27C7 chip. The B+HCCES module operates at a fixed sampling frequency of 300 MHz, generated by an embedded phase-locked loop. The B+HCCES module demonstrates an enhanced throughput of 3.33 times compared to the state-of-the-art, while still maintaining a comparably lightweight architecture. The experimental results demonstrate that the generated random sequence successfully passes the NIST SP800-90B and BSI AIS-31 tests.

Keywords

• True random number generator (TRNG)
• race hazard
• ring oscillator
• field programmable gate array (FPGA)
• jitter