Design of standardized universal simulation test platform for onboard solid state memory controllers

Abstract

The increasing functionality and complexity of electronic systems places higher demands on the efficiency of system verification tests. The traditional satellite test platform is customized according to the specific model task. Its design and development cycle is long, and the comprehensive cost is difficult to adapt to the current task requirements. To this end, this paper proposes a general simulation test platform architecture for on-board solid-state storage controller based on System Verilog. It uses a hierarchical model internally, and the signal interface uses APB bus standard uniformly. It can be configured by testing the platform data source and format to adapt to onboard solid-state storage controllers of different capacities, different rates and different configurations. Experiments show that the test platform designed in this paper has certain versatility, which can effectively save test time and improve test coverage compared with traditional test platform.

Keywords

• onboard
• solid state memory controllers
• test platform
• system verilog