DCryp-Unit: Crypto Hardware Accelerator Unit Design for Elliptic Curve Point Multiplication

Abstract

We propose a hardware-optimized design that implements a Montgomery Elliptic-curve point multiplication Algorithm over $GF(2^{233})$ using Lopez-Dahab projective coordinates. Moreover, we propose a digit-parallel modular multiplier, which reduces clock cycles and improves throughput. Also, we provided how to use our proposed digit-parallel multiplier for post-quantum cryptography algorithms. In addition, we use the proposed digit-parallel multiplier with the square circuit to implement the Itoh-Tsujii inversion algorithm for modular inversion computation; this permits hardware resource minimization. An efficient finite-state machine controller is implemented for control functionalities. A figure of merit in throughput/area is defined for reasonable comparison to state-of-the-art. We provide implementation results after post-place-and-route on field-programmable gate array devices. On the Virtex-7 device, our design utilizes 3386 slices and requires 7218 clock cycles; it achieves a maximum frequency of 365 MHz and computes one point multiplication in $19.77\mu s$ . The total power consumption of our design is 2027 mW. The calculated values for throughput and figure of merit are 50.58Kbps and 14.93, respectively. Consequently, the implementation results and comparisons reveal our design’s suitability for applications requiring area and throughput-optimized cryptographic implementations.

Keywords

• Binary elliptic curves
• point multiplication
• hardware design
• implementation
• FPGA