Design and Implementation of Bridgeless Power Factor Corrector with Low Static Losses

Abstract

Research and development of power factor corrector (PFC) for AC/DC converters of single-phase AC power supply network are discussed within this article. Two-channel bridgeless PFC is proposed in this paper. The proposed converter allows us to lower current DC component generation in the power network and to reduce static and dynamic losses of semiconductor devices. The suggested solution characteristic features are the absence of a diode bridge while using two identical converters operating in different power network voltage half periods. Due to cumulative chokes in each converter, the function setting the consumption current sinusoidal form is realized with the ability of wide-range output voltage regulation. A number of Simulink-models have been developed in order to study operating modes and to test control algorithms of the proposed bridgeless PFC. The input current harmonic content, efficiency coefficient, passive elements’ electrical parameters, and output voltage pulsation coefficient of the proposed bridgeless PFC were researched by Simulink-models. The results obtained show the efficiency of the proposed solutions regarding PFC. The THD value does not exceed 1.3% in steady state mode and is not over 4% during the voltage stabilization process; the minimal value of the output voltage pulsation coefficient is 3.1%. The suggested solutions can be applied in accumulator batteries’ charging sets and DC motors’ reduced-current start.

Keywords

• power factor correction
• AC/DC power converter
• static losses
• total harmonic distortion
• sinusoidal current