DESIGN OF A LOW-POWER AND HIGH THROUGHPUT ERROR DETECTION AND CORRECTION CIRCUIT USING THE 4T EX-OR METHOD

Abstract

This paper describes an efficient implementation of an error correction circuit based on single error detection and correction with check bit pre-computation. The core component of the proposed 4-bit EX-OR circuit was designed using the CMOS cascade method. This paper presents a 4-input EX-OR gate that was developed from a 2-input EX-OR gate using the bit slice method. The proposed architecture retains the modified Error Correction Code (ECC) circuit. The proposed 4-input EX-OR gate and its auxiliary components such as AND, MUX and D Flip-Flop were schematized using the DSCH tool and the layouts was analysed using the BSIM4 analyser. The simulation results were obtained and compared with the performance of existing circuits. LVS verification was performed on the modified ECC circuit at CMOS 70 nm feature size and its corresponding voltage of 0.7V. The modified ECC circuit simulation results were analysed and compared with the performance of existing circuits in terms of propagation delay, power dissipation, area, latency, and throughput. The proposed ECC circuit showed an improved performance with existing circuit low power dissipation (94.41%) and high throughput (95.20%).

Keywords

• EX-OR gate
• ECC
• MUX
• Power dissipation
• Propagation delay
• Throughput
• BSIM 4