Fractional‐N multiplying delay‐locked loop with delay‐locked loop‐based injection clock generation

Abstract

A fractional‐N multiplying delay‐locked loop (MDLL) with delay‐locked loop (DLL)‐based injection clock generation is presented. By exploiting multiphase output of DLL which delay is locked to the period of output frequency, the proposed architecture performs a fractional clock multiplication with MDLL, while eliminating deterministic jitter from fractional divider. The proposed MDLL is designed in a 0.18 μm CMOS process and achieves 31.25 kHz frequency resolution with 1 MHz reference frequency. It occupies an active area of 0.055 mm2, and consumes 45 μW for 10 MHz frequency generation, showing energy efficiency figure‐of‐merit (FoM) of 4.5 μW/MHz.

Keywords

• fractional‐N multiplying delay‐locked loop
• delay‐locked loop‐based injection clock generation
• multiphase output
• output frequency
• fractional divider
• CMOS