An implementation method of missile speed compensation with FPGA on high speed moving platform

Abstract

In view of real-time demand for speed compensation on high speed moving platform, an implementation method of missile speed compensation is proposed. After the idea of range cell migration compensation applied to the missile speed compensation, the signal-to-noise ratio of coherent accumulation is improved, and hardware design is realized on FPGA. The simulation experiment shows that the missile speed compensation method with FPGA has advantages of high real-time, fast processing speed and high precision.

Keywords

• RCMC
• FPGA
• radar
• hardware implementation