Input-parallel output-series Si-SiC hybrid inverter with fractional harmonic elimination

Abstract

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This paper proposes an input-parallel output-series (IPOS) Si-SiC hybrid inverter with dual-frequency harmonic elimination modulation strategy. The proposed topology composed of two power conversion cells and a three-phase five-column medium-frequency step-down transformer, the low-frequency power conversion cell (LFPC-C, 1 kHz) leverages strong current-carrying capacity of silicon-based devices for dealing with the system main power, and the high-frequency power conversion cell (HFPC-C, 30 kHz) based on wide-bandgap semiconductor SiC devices is used to addressing the fractional harmonics compensation power. This topology combines the strong current carrying capability of Si devices with the low switching loss of SiC devices at high frequency and achieves high quality power conversion at low cost and low loss. Compared to existing “IPOP” Si-SiC hybrid inverters, this topology adopts a coupling step-down transformer on the output side of both LFPC-C and HFPC-C, which can effectively reduce current stress of HFPC-C SiC devices. Additionally, a dual-frequency harmonic elimination modulation strategy based on the topology is proposed to solve the fractional harmonics caused by the LFPC-C. The paper establishes a mathematical model according to the harmonic distribution characteristics of the LFPC-C and HFPC-C, and designs the system control schedules. Building upon the derivation of the voltage ripple model and the design of hardware parameters, Si IGBT and SiC MOSFET were selected for constructing a 7.5 kW prototype for testing, and the experimental results validate the feasibility of this topology and the accuracy of theoretical analysis.

Keywords

• fractional power processing
• harmonic compensation
• dual-frequency harmonic elimination modulation strategy
• multiple quasi-proportional resonance control
• recursive discrete fourier transform
• SHEPWM