A Synchronization Shift Phase-Locked Loop Strategy for Three-Phase Grid-Tied Inverters Under Unbalanced Grid Voltage Scenarios

Abstract

The phase-locked loop (PLL) is one of the most commonly used approaches for the inverter to achieve grid-connected operation. However, when unbalanced grid voltages occur, the double-line frequency oscillation exists in the system. With the conventional PLL method, the synchronous reference frame (SRF) voltage will be oscillated because of the double-line frequency oscillation. As a result, the electrical angle of the grid cannot be estimated accurately. Moreover, inverter output currents will be distorted and the current total harmonic distortion (iTHD) will be increased. To solve this issue, an enhanced synchronization shift phase-locked loop (SSPLL) strategy is proposed in this paper. With the proposed SSPLL, the inherent double-line frequency oscillation in the control loop can be eliminated. Therefore, the electrical angle of the grid can precisely be calculated, whereas the current THD can be suppressed. The developed SSPLL can be realized by the digital signal processor (DSP) without adding extra circuits and components. Comprehensive theoretical analysis and mathematical derivations of the SSPLL are also revealed. Eventually, both simulation and experimental results obtained from a 5kVA prototype circuit will be presented to verify the performance and feasibility of the proposed SSPLL. Compare to conventional PLL methods, a maximum 65.22% improvement of current THD and a maximum 51.2% improvement of the controller execution time can be achieved with the proposed strategy.

Keywords

• Three-phase grid-tied inverter
• phase-locked loop
• unbalanced grid voltages