Review of ferroelectric field‐effect transistors for three‐dimensional storage applications

Abstract

Abstract The ferroelectric field‐effect transistor (FeFET) is one of the leading contenders to succeed charge‐trap‐based flash memory (CTF) devices in the current vertically‐integrated NAND flash storage market. The operation of a FeFET is based on the field‐effect in the channel of the FET that is exerted by the uncompensated ferroelectric bound charge, which is also the fundamental source of the depolarization effect. This paper briefly reviews the current status of CTF‐based NAND flash memory as a benchmark for FeFET. Then, a one‐dimensional model based on a load‐line analysis of FeFET technology is presented. The paper subsequently deals with the two‐dimensional domain effect in nano‐sized NAND‐type FeFET devices. While NAND‐type FeFET operation is likely, current ferroelectric materials with high remanent polarization (Pr) of ∼10 μCcm‐2 and coercive field (Ec) of ∼1 MVcm‐1 are not feasible for use in such devices. This is fundamentally due to the high depolarization field induced by the unnecessarily high Pr, which not only destabilizes the memory state but also induces a severe interference effect between neighboring cells. Therefore, a new ferroelectric material with a moderately low Pr and higher Ec > ∼3 MVcm‐1 is necessary, along with structural innovation to minimize the interference effect.

Keywords

• depolarization
• domain pattern
• ferroelectric field‐effect transistor
• interference
• NAND architecture