Scalable Fully-Coupled Annealing Processing System Implementing 4096 Spins Using 22nm CMOS LSI

Abstract

Annealing processors specialized for combinatorial optimization problems are attracting attention. Although a general-purpose fully-coupled type is required for annealing processors in CMOS, the complexity of the coupling has led to scalability issues. Therefore, a scalable structure has been proposed that divides the calculation into multiple chips and has already been verified by using FPGAs. In the proposed system, 4,096 spins are implemented on a single board by 36 22-nm CMOS LSIs (512-spin fully-coupled annealing processor) and 1 FPGA for control. This is the largest fully-coupled annealing processing system implemented on a single board. This paper describes two main techniques used in the proposed system. The first is an approximate halving of the number of chips (from 64 to 36) by reducing the interaction matrix, and the second is an 8-parallel-solution search by parallel operation after reducing the number of chips. We found that a single LSI and a control FPGA can operate as a 512-spin fully-coupled annealing processor. Compared with CPU, the proposed system with 36 LSIs and control FPGAs improves computation speed by a factor of 34.0 and power performance by a factor of 2,344, while searching for 8 solutions in parallel.

Keywords

• Annealing processor
• simulated annealing
• scalable
• interaction reduction
• Ising machine