Capacitor Voltage Imbalance Mechanism and Balancing Control of MMC When Riding Through PTG Fault

Abstract

Modular multilevel converter (MMC) based fault ride through (FRT) control is a promising solution to deal with the pole-to-ground (PTG) fault in high voltage direct current (HVDC) system. However, when MMC switches to the FRT control, capacitor voltage imbalance between upper and lower arms will occur, resulting in the deterioration of FRT performance. This letter provides a comprehensive analysis for the imbalance issue from the perspective of fundamental frequency circulating current (FFCC). It is found the imbalance during FRT stage will not expand continuously, but converge to a certain value gradually. The specific imbalance degree is closely associated with the amplitude of FFCC. In order to solve the imbalance issue, an open-loop balancing control is proposed. By introducing a fundamental frequency feedforward item to the inherent circulating current control, the proposed method can not only balance the capacitor voltages, but also minimize the amplitude of FFCC, and consequently the power loss of MMC during FRT process can be reduced. Finally, simulation results of PSCAD/ EMTDC verify the validity of theoretical analysis.

Keywords

• Balancing control
• capacitor voltage imbalance
• FFCC
• FRT control
• HVDC system
• PTG fault