A Memristive Cell with Long Retention Time in 65 nm CMOS Technology

Abstract

Abstract The memristor, which Leon Chua discovered in 1971 and Hewlett Packard fabricated for the first time in 2008, is still facing many design and fabrication challenges. Luckily, memristor emulators using mature Complementary Metal Oxide Semiconductor (CMOS) processes are good substitutes for memristors in several applications. The common setback for these emulators is their inability to retain their internal states for long periods of time. This article presents a memristive cell that not only has the memristor's characteristics but also can retain its resistance for up to 10 years. To bring forward such a cell, a charge trap in a 1 mm2 chip is designed and fabricated using a standard 65 nm CMOS process. By characterizing the proposed trap prototype, its unexpected yet interesting behavior is revealed, such as charge tunneling that occurrs at voltages between 350 mV and 650 mV despite the process sensitivity. Next, based on the measurement results and using the VerilogAMS programming language, the charge trap to be combined with other circuits that constitute the proposed memristive cell is modeled. This model, which is partly based on previously reported models, matches the measured characteristics of the fabricated charge trap and can be easily integrated into circuit simulations.

Keywords

• charge traps
• long data retention time
• memristive cells
• memristor emulators
• memristors