Asynchronous interface circuit for nonlinear connectivity in multicore spiking neural networks

Abstract

To expand the scale of spiking neural networks (SNNs), an interface circuit that supports multiple SNN cores is essential. This circuit should be designed using an asynchronous approach to leverage characteristics of SNNs similar to those of the human brain. However, the absence of a global clock presents tim-ing issues during implementation. Hence, we propose an intermediate latching template to establish asynchronous nonlinear connectivity with multipipeline processing between multiple SNN cores. We design arbitration and distribu-tion blocks in the interface circuit based on the proposed template and fabri-cate an interface circuit that supports four SNN cores using a full-custom approach in a 28-nm CMOS (complementary metal-oxide-semiconductor) FDSOI (fully depleted silicon on insulator) process. The proposed template can enhance throughput in the interface circuit by up to 53% compared with the conventional asynchronous template. The interface circuit transmits spikes while consuming 1.7 and 3.7 pJ of power, supporting 606 and 59 Mevent/s in intrachip and interchip communications, respectively.

Keywords

• asynchronous
• connectivity
• interchip communication
• interface circuit
• intrachip communication
• nonlinear connectivity
• spiking neural network