Design and FPGA Implementation of a Novel Efficient FRM-Based Channelized Receiver Structure

Abstract

The main application of the filter bank in radar signal processing is the wideband digital channelized receiver. In order to save hardware resources of the field programmable gate array (FPGA), the efficient channelized receiver structure using polyphase filter has been designed. However, when the number of channels is greatly increased or the transition bandwidth of the filter bank (FB) becomes very narrow, it still consumes large amounts of hardware resources. Therefore, a novel efficient channelized receiver structure based on frequency response masking (FRM) and modulation filter bank is proposed in this paper. The proposed novel structure has less computational complexity in implementing FB with narrow transition bandwidth (NTB). Compared with other efficient FRM-based structures, the proposed novel structure is more suitable for wideband digital channelization receiver. The proposed novel structure is verified correctly by Matlab simulation. The FPGA implementation of the polyphase channelized receiver structure and the proposed novel efficient FRM-based channelized receiver structure are completed by Xilinx System Generator. The result shows that the proposed novel efficient FRM-based channelized receiver structure can save 48.09% of the DSP48E1 hardware resources compared with the polyphase channelized receiver structure and has low group delay characteristic.

Keywords

• Frequency response masking
• narrow transition bandwidth
• channelized receiver
• field programmable gate array