Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

Abstract

Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology computer-aided design (TCAD) device simulation data of GAA field-effect transistors (FETs) subjected to both tensile and compressive strain in nMOS and pMOS devices. Strain was induced into the channel via lattice mismatch between the channel and source/drain epitaxial regions, as simulated by 3D TCAD process simulator. The transport models were calibrated against advanced Monte Carlo simulations to ensure accuracy. The resulting neural compact model demonstrated a close approximation to the original simulation results, achieving a minimal error of 1%. To assess the strain effect on circuit-level performance, SPICE simulations were conducted for a 5-stage ring oscillator and a 2-input NAND gate using the neural compact model. The propagation delay of the 5-stage ring oscillator improved from 3.60 ps to 2.85 ps when implementing strained GAA FETs. Also, strain enhanced the power-delay product of the 2-input NAND gate by 13.8% to 15.5%, depending on the input voltage sequence.

Keywords

• Strain engineering
• gate-all-around CMOS
• neural compact model
• circuit performance