A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing

Abstract

This work presents a small-area 2nd-order continuous-time $\Delta \Sigma $ Modulator (CT $\Delta \Sigma \text{M}$ ) with a single low dropout regulator (LDO) serving as both the power supply for the CT $\Delta \Sigma \text{M}$ and reference voltage buffer. The CT $\Delta \Sigma \text{M}$ is used for digitising very low amplitude signals in applications such as magnetic tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This enables a single low-dropout (LDO) voltage regulator to generate both power supply and $\text{V}_{ref}$ for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CT $\Delta \Sigma \text{M}$ consumes $300 ~\mu \text{W}$ of power when clocked at 10.24 MHz. The CT $\Delta \Sigma \text{M}$ achieves a state-of-the-art area of 0.07 mm2.

Keywords

• Analog-to-digital conversion
• continuous-time delta-sigma modulation
• excess loop-delay compensation
• FIR DAC
• magnetic sensor
• sensor interface