Design of efficient N‐bit shift register using optimized D flip flop in quantum dot cellular automata technology

Abstract

Abstract There is a need for secure and powerful nano communication systems with ultra‐low power consumption in the new digital age. Quantum‐dot cellular automata (QCA) is a technology which can be used for designing these systems. In the nano regime, relative to complementary metal oxide semiconductor technology, QCA is able to work with greater speed and lower power dissipation along with high density. This study examines the applicability and viability of using QCA to construct the sequential circuits. An optimized D flip flop is designed in QCA. The fault tolerance for single cell omission and single cell addition defects of the proposed flip flop is also presented. This flip flop is then used to design 2‐, 3‐, 4‐ and 8‐bit shift registers which can be efficiently scaled up to N‐bits. The operations of all proposed designs are validated using QCADesigner tool and the energy dissipation analysis is done using QCAPro tool. The performance comparison shows that the proposed QCA designs are cost efficient and they can be utilized efficiently in designing digital communication systems which require small area along with high speed and ultra‐low power consumption.

Keywords

• cellular automata
• fault tolerance
• flip‐flops
• logic circuits
• logic design
• power consumption