Digital Fixed-Point Low Powered Area Efficient Function Estimation for Implantable Devices

Abstract

This article introduces a new multiplier-less 32-bit fixed point architecture for estimating complex non-linear functions based on adapted shift only series expansions. This novel hardware structure has been proposed for use as a dedicated core unit in implantable medical devices. Its implementation in FPGA produces a mean squared error of 0.23% over the functions $sin(x), cos(x), e^{ix}$ and $tan^{-1}(x)$ when compared to unrestricted CPU implementations. These results are achieved with the use of only 133 sliced registers and 399 Look-up-tables (LUTs). Furthermore, the hardware performs extremely well in our hardware-in-the-loop real use case application for the detection of epilepsy by correctly detecting true positive seizures. When implemented into 130 nm technology via GOOGLE Sky130 PDK and Openlane EDA tools, the ASIC occupies a space of $0.0625~mm^{2}$ which represents a 47% reduction when compared to competitors. In addition, its power consumption is reduced to 6.46 mW at 100 MHz $f_{o}$ and just $0.4~\mu \text{W}$ at 1KHz $f_{o}$ .

Keywords

• Low power
• area optimisation
• integrated circuits
• function approximation
• hardware
• phase locking value