Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory

Abstract

Abstract Three-terminal (3-T) thyristor random-access memory is explored for a next-generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate–cathode voltage (V GC,ST) and anode–cathode voltage (V AC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized V GC,ST of − 0.4 V and V AC,ST of 0.6 V shows the continuous data retention capability without refresh operation with a low standby current of 1.14 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on unselected cells by adjusting gate–cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.

Keywords

• Capacitorless 1T DRAM
• Memory array operation
• Memory disturbance
• Three-terminal TRAM
• Gated-thyristors