Influence of Parasitic Capacitance on Output Voltage for Series-Connected Thin-Film Piezoelectric Devices

Abstract

Series-connected thin film piezoelectric elements can generate large output voltages. The output voltage ideally is proportional to the number of connections. However, parasitic capacitances formed by the insulation layers and derived from peripheral circuitry degrade the output voltage. Conventional circuit models are not suitable for predicting the influence of the parasitic capacitance. Therefore we proposed the simplest model of piezoelectric elements to perform simulation program with integrated circuit emphasis (SPICE) circuit simulations). The effects of the parasitic capacitances on the thin-film Pb(Zr, Ti)O3, (PZT) elements connected in series on a SiO2 insulator are demonstrated. The results reveal the negative effect on the output voltage caused by the parasitic capacitances of the insulation layers. The design guidelines for the devices using series-connected piezoelectric elements are explained.

Keywords

• output-voltage enhancement
• SPICE
• parasitic capacitance
• piezoelectric thin films
• MEMS