The Design of a Low-Noise, High-Speed Readout-Integrated Circuit for Infrared Focal Plane Arrays
Yusong Mu,
Zilong Zhao,
Chong Chen,
Di Yuan,
Jing Wang,
Hansong Gao,
Yaodan Chi
Affiliations
Yusong Mu
Key Laboratory for Comprehensive Energy Saving of Cold Regions Architecture of Ministry of Education, College of Electronic and Computer, Jilin Jianzhu University, Changchun 130118, China
Zilong Zhao
Key Laboratory for Comprehensive Energy Saving of Cold Regions Architecture of Ministry of Education, College of Electronic and Computer, Jilin Jianzhu University, Changchun 130118, China
Chong Chen
Key Laboratory for Comprehensive Energy Saving of Cold Regions Architecture of Ministry of Education, College of Electronic and Computer, Jilin Jianzhu University, Changchun 130118, China
Di Yuan
Changchun Jingyi Optoelectronic Technology Co., Ltd., Changchun 130103, China
Jing Wang
Key Laboratory for Comprehensive Energy Saving of Cold Regions Architecture of Ministry of Education, College of Electronic and Computer, Jilin Jianzhu University, Changchun 130118, China
Hansong Gao
Key Laboratory for Comprehensive Energy Saving of Cold Regions Architecture of Ministry of Education, College of Electronic and Computer, Jilin Jianzhu University, Changchun 130118, China
Yaodan Chi
Key Laboratory for Comprehensive Energy Saving of Cold Regions Architecture of Ministry of Education, College of Electronic and Computer, Jilin Jianzhu University, Changchun 130118, China
This paper describes the design of a low-noise, high-speed readout-integrated circuit for use in InGaAs infrared focal plane arrays, and analyzes the working principle and noise index of the pixel circuit in detail. The design fully considers the dynamic range, noise, and power consumption of the pixel circuit in which a capacitance transimpedance amplifier structure is adopted as the input stage circuit, and chip fabrication via an XFAB 0.18 µm CMOS process is successfully realized. The ROIC adopts monolithic integration and implements various functions, such as windowing, subsampling, and different integration and readout modes. The ROIC reached an array scale of 32 × 32, a frame rate of 100 Hz, and a readout rate of 20 Mbps with an analog power consumption of less than 52 mW. The measurement results show that the input reference noise can be reduced to 143 e- via the CDS, and the fully customized scheme has certain advantages in the research of high-performance ROICs.
