A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis

Abstract

This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise and low-power circuit design methodologies and aggressive voltage scaling to satisfy both the low power consumption and low input-referred noise requirements of ECG signal acquisition systems. The AFE was realized with a three-stage fully differential AC-coupled amplifier, and it provides bio-signal acquisition with programmable gain and bandwidth. The AFE was implemented in a 130 nm CMOS process, and it has a measured tunable mid-band gain from 31 to 52 dB with tunable low-pass and high-pass corner frequencies. Under only 0.5 V supply voltage, it consumes 68 nW of power with an input-referred noise of 2.8 µVrms and a power efficiency factor (PEF) of 3.9, which makes it very suitable for energy-harvesting applications. The low-noise 68nW AFE was also integrated on a self-powered physiological monitoring System on Chip (SoC) that is used to capture ECG bio-signals. Heart rate extraction (R-R) detection algorithms were implemented and utilized to analyze the ECG data received by the AFE, showing the feasibility of <100 nW AFE for continuous ECG monitoring applications.

Keywords

• analog front end (AFE)
• electrocardiogram (ECG)
• IoT
• sub-threshold operation
• ultralow power