A Robust LC-<i>π</i> Matching Network for 112 Gb/s PAM4 Receiver in 28 nm CMOS

Abstract

This article presents analysis, design details, and simulation results of an impedance matching network designed for a 112 Gb/s pulse-amplitude-modulation-4 (PAM4) receiver using an LC-π structure. We designed the bonding wire as a part of the matching network, which reduced design pressure on the equalizer as there will be no need to compensate the loss of the chip package. To avoid robustness issues caused by the fluctuation of the bonding wire inductance, the matching network is designed to bw adjustable by the capacitance on PCB and the terminal resistance. We analyzed the parasitics in the layout and the influence of nearby and dummy metals and obtained reliable simulation results through electromagnetic field simulation. This matching network is designed with a 28 nm CMOS process. Post-layout simulation results show that with bonding wire inductance changing from 150 pH to 250 pH, it can always meet CEI-112G-XSR-PAM4 Extra Short Reach Interface requirements.

Keywords

• wireline receiver
• broadband impedance matching
• LC passive filter
• bonding wire
• robustness