A Single-Stage 12-Times Frequency Multiplier for a 5G Frequency Synthesizer

Abstract

This paper presents a single-stage 12-times frequency multiplier composed of an invented harmonic generator (HG) and a modified cascode buffer. The reliable output frequency band is guaranteed from 16 GHz to 28 GHz (54.5% frequency range). The whole band is divided to 256 subsidiary frequency bands by applying 8-bit digitally controlled capacitor banks of LC (inductor and capacitor)-tuned output. The invented HG architecture is based on a double-balanced mixer, but the bottom and top differential pairs are appropriately biased to generate the required turn-on time, τ, for obtaining the more dominant desired 12th harmonic. In addition, to reduce power consumption and conversion gain variation for the target frequency band, a negative-gm differential pair is added to the HG core in parallel to enhance the equivalent parasitic resistance, which is directly proportional to the HG gain. Newly created automatic constant amplitude control is able to keep the HG amplitude output constant as well as keep it from oscillating. Further desired harmonic amplification and unwanted suppression can be achieved by the proposed cascode buffer. The proposed 12-times multiplier is fabricated on a 65-nm CMOS (complementary metal-oxide-semiconductor) process and successfully tested. Chip die size is 0.4 mm2, and power consumption is only 4 mW.

Keywords

• double-balanced mixer (dbm)
• frequency multiplier
• harmonic suppression ratio
• millimeter wave
• 5g synthesizer