Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips

Abstract

Existing methods for clock domain crossing (CDC) design were used directly in a system-on-chip (SoC),which result in high design and verification complexity.To solve this problem,a design method was proposed.It separated CDC design completely from functional design and transmits all the CDC signals in an IP design with the help of an independent and dedicated CDC processing module.It also scaled down the total number of CDC signals to two groups of opposite directions through encapsulating point-to-point communication interface as well as processing CDC signals of the same direction in combination.Experiment results demonstrate that this method is able to sharply reduce the verification complexity of CDC design and also simplify the whole SoC design,without significant adding to transfer delay or area cost of an IP design.

Keywords

• system-on-chip;clock domain crossing design;verification complexity;communication interface