New design approaches of reversible BCD encoder using Peres and Feynman gates

Abstract

This paper proposes two new design approaches for decimal to binary-coded-decimal (BCD) encoder using reversible logic through Peres gate (PG) and Feynman gate (FG) which consume 10 and 11 gates respectively to realize such circuitry. Gates have been arranged properly to minimize the gate count (GC) followed by the reduction of the quantum cost (QC) and garbage outputs (GO). The proposed designs have an improvement at least up to ∼45%, ∼40%, and ∼50% of GC, GO and QC respectively from the best state of the art designs. Keywords: Binary-coded-decimal (BCD), Feynman gate (FG), Garbage output (GO), Gate count (GC), Peres gate (PG)