3D MICROPACKAGING OF INTEGRATED CIRCUITS

Abstract

A major paradigm change, from 2D IC to 3D IC, is occurring in microelectronic industry. Joule heating is serious in 3D IC, and vertical interconnect is the critical element to be developed. Also, reliability concerns will be extremely important: electromigration and stress-migration. This paper presents some actual problems and reliability challenges in 3D IC packaging technology. It shows how different architectures have evolved to meet the specific needs of different markets: Multi Chip Module (MCP); Multipackage module (MPM); Embedded SIP modules; SIP package-on-package (PoP) modules; EMIB (Embedded Multi-die Interconnect Bridge); Silicon-based SIP-Module; 3D-TSV stacked module; SIP variants with combinations of wideband and flip-chip interconnects. Causes of blockages and failure mechanisms, as well as problems with predictive reliability, which will need to be developed in the coming years, are analysed.

Keywords

• prototypage virtuel
• moore's law
• analyse des compromis
• reliabilit