Design of Parallel Analog to Digital Converter Based on Darlington CMOS Inverter

Abstract

This article presents a 4-bit parallel analog-to-digital converter was designed by using Darlington CMOS Inverter which is operated in accordance with CMOS threshold voltage. Thus, there is no need to use resistance array block for obtaining quantization voltage in this structure. Generally, the darlington structure is used on bipolar junction transistor circuits, however it is proposed for CMOS circuits in this study. Hence, the gain of inverter circuit increases. According to simulation results, power consumption is 96.6mW, DNL and INL errors are (-0.71/+0.82)LSB and (0/-1.24)LSB respectively. The provided power consumption, DNL and INL measures are observed at 100MHz input with 10GS/s sampling rate. All the simulation results were obtained from schematic circuits.

Keywords

• Darlington CMOS Inverter
• Analog-to-Digital Converter
• Parallel A/D Converter