Dynamic partial reconfiguration scheme for fault-tolerant FFT processor based on FPGA

Abstract

The fast Fourier transform FFT processor is an important part of the space real-time signal processing system based on field programmable gate array (FPGA). Since occupying a large amount of logical resources and storage resources, FFT processor is more vulnerable to high-energy particles in space, resulting in single event upset (SEU). This paper presents a novel FPGA scrubbing framework base on dynamic partial reconfiguration technique for a FFT processor to mitigate SEU. The proposed scheme is compared with the blind scrubbing, the reconfiguration time is reduced by 78%. Then, the resource utilisation is 61.5% less than triple modular redundancy scheme. This paper also presents a DPR controller for FFT processor, which is evaluated in terms of hardware resources and reconfiguration time. A comparison to the Xilinx PRC IP shows that multipath delay feedback FFT controller saves 38.6% resources.

Keywords

• field programmable gate arrays
• fault tolerant computing
• fast fourier transforms
• redundancy
• radiation hardening (electronics)
• microprocessor chips
• reconfiguration time
• multipath delay feedback fft controller
• dynamic partial reconfiguration scheme
• fault-tolerant fft processor
• field programmable gate array
• logical resources
• storage resources
• dynamic partial reconfiguration technique
• fast fourier transform fft processor
• novel fpga scrubbing framework
• high-energy particles
• triple modular redundancy scheme
• dpr controller
• blind scrubbing
• xilinx prc ip
• single event upset