Analysis and Design of High Order Active Filter Circuit

Abstract

In analog sampling circuits, filters are essential for processing sampled signals before they are sent to DSP for further processing, to avoid clutter interference on them. This practice often reduces the hardware requirements for analog sampling channels. Compared to passive filters, active filters exhibit stable amplification and frequency characteristics with load changes. Therefore, they are more widely used in small signal processing circuits. However, designing high-order active filters often leads to discrepancies between theoretically calculated values and simulated outcomes, resulting in circuit parameters that fall short of the requirements of device selection. This study started from the analysis of second-order active filters, focusing on the transfer function, which revealed the cause of the above design annoyance, i.e. variations in the system damping coefficient. To address this challenge, two solutions were proposed to manipulate the system damping coefficient respectively by changing system gains and adjusting the ratio of the two capacitance values in filter circuits. Through further analysis and calculations, this study derived the system damping required for each second-order filter circuit within a high-order filter constructed using these two solutions. Furthermore, a PSPICE simulation analysis was performed using 4-order and 8-order filters with a cut-off frequency of 100 kHz designed following the proposed methodology. The resulting simulated cut-off frequency values of 98.828 kHz and 96.200 kHz, respectively, closely matched the theoretical calculations, verifying the effectiveness of the proposed design approach for high-order filters.

Keywords

• high-order active filter
• analog sampling
• cut-off frequency
• pspice
• damping coefficient