Addressing Mode Extension to the ARM/Thumb Architecture

Abstract

In this paper, two new addressing modes are introduced to the 16-bit Thumb instruction set architecture to improve performance of the ARM/Thumb processors. Contrary to previous approaches, the proposed approach focuses on the addressing mode of the instruction set architecture. It adopts scaled register offset addressing mode and post-indexed addressing mode from the 32-bit ARM architecture, which is the superset of the 16-bit Thumb architecture. To provide the encoding space for the new addressing modes, the register fields in the LDM and STM instructions are reduced, which are not frequently executed. Experiments show the proposed extension achieves an average of 7.0% performance improvement for the seven benchmark programs when compared to the 16-bit Thumb instruction set architecture.

Keywords

• computer architecture
• computer performance
• high performance computing
• instruction set design
• microprocessors