Chip packaging interaction of SiC junction barrier Schottky diode packages

Abstract

Wide band gap semiconductors are attractive in the electric vehicle industry because of their higher operating temperatures, and lower switching losses than those of silicon semiconductors. However, the electric vehicle industry has driven the development of more reliable semiconductors because of safety issues. Among several reliability issues, the reliability at the chip level can be a challenging problem because chip-related failures are difficult to observe in the early design stage. In this study, the chip package interaction for a silicon carbide (SiC) junction barrier Schottky diode package was investigated to estimate the stresses of the chip layers at the package level. This methodology will help power semiconductor manufacturers perform a robust design of their packages in terms of SiC chip reliability. Moreover, the response surface methodology can be used to establish a correlation between the maximum stresses of the passivation layer and three-wire bonding conditions. This methodology can be used to determine optimal wire-bonding conditions to improve chip reliability.

Keywords

• Chip package interaction
• SiC junction barrier schottky diode
• Finite element analysis
• Submodeling technique
• Response surface method