Design of high-speed and low-latency Viterbi decoder

Abstract

In a Viterbi decoder, there are two known memory organization techniques for the storage of survivor sequences, namely register exchange method and traceback method. This paper presents a new survivor path storage scheme that enables short latency in area-efficient Viterbi decoder. This is achieved by introducing part register exchange method into traditional traceback method. Since more path information is read per clock,the traceback time is largely shortened, and the path memory size is also saved greatly. On contrast to conventional register exchange and traceback method, the new method has obvious advantage of hign speed,low resource cost and low-latency.

Keywords

• convolutional code
• Viterbi
• FPGA
• TB
• RE