Vedic algorithm for cubic computation and VLSI implementation

Abstract

Algorithm of cubic computation and its VLSI implementation is described in this paper through ‘Vedic mathematics’ formulae. An N-bit cubic implementation circuit was structured into two cubic subgroups (bit length = N2 or lesser), multiplier and adder. VLSI aspects such as propagation delay and dynamic power consumption of such circuitry were lessened down notably by reducing the number of partial products. Designs implementation and estimation of performance parameters: delay and power consumption were figured out by spice spectre with 90 nm CMOS technology. The estimated values for propagation delay and power consumption of the reported 8-bit cubic circuitry were ∼5.5 ns and ∼2.6 mW respectively. Propagation delay has been enhanced by ∼12% and power consumption dropped down by ∼22% in comparison to its counterpart (traditional architecture).

Keywords

• Anurupyena
• Cubic
• High speed
• Vedic mathematics
• Yavadunam sutra (YVDN)