Common-Mode Voltage Mitigation for Dual Three-Phase Three-Level ANPC Inverters Using Dynamic Phase-Shift PWM

Abstract

In this study, a common-mode voltage (CMV) reduction scheme based on carrier-based pulse-width modulation (PWM) is proposed for asymmetric dual three-phase hybrid active neutral-point-clamped (ADTP-HANPC) inverters. The fundamental concept is that the alignment sequence of multi-level gating signals is adjusted to produce zero CMV or ones with equal magnitude and opposite polarities in the two individual loads. To achieve this objective, dynamic phase-shift PWM (DPSPWM) is implemented between the switches of the DTP-HANPC inverter. The DPSPWM outperforms existing CMV elimination methods in terms of efficiency, with a 20 % improvement. This is primarily owing to the lower number of switching transitions. Furthermore, the current and voltage THDs are reduced compared with the existing zero CMV space vector PWM (SVPWM). The effectiveness of the proposed method has been validated through simulations and experiments. These demonstrated a significant reduction (≥75.9%) in maximum CMV peaks.

Keywords

• Common-mode voltage (CMV)
• dual three-phase (DTP)
• hybrid active neutral point clamped (HANPC)
• pulse-width modulation (PWM)