AVLS-based 32/33 Pre-scaler for frequency dividers

Abstract

Pre-scalers are widely used in phase-locked loops (PLL) which are vital components in communication systems. The Dual Modulus Pre-Scaler (DMPS) has dual division capability, to divide the clock by N/N+1 cycles, which can be controlled by the designer based on the control circuitry. Pre-scaler circuits are used to divide the received signal to obtain integer multiples of the received signal. This paper proposes a power efficient 32/33 pre-scaler for high-frequency operation. DMPS is composed of a series of D Flip-flops (D-FF) and logic gates along with feedback connection between the different stages. Clock skew is of major concern in the D-FFs, which can be reduced by realizing D-FFs using true single-phase clock (TSPC) logic. Furthermore, the incorporation of an Adaptive Voltage Level Source (AVLS) circuit decreases the power consumption of the circuits. By integrating the AVLS circuit to divide-by-32/33 DMPS, low power consumption is achieved. At different operating frequencies, both divide-by-32 and -33 modes of the proposed 32/33 DMPS with AVLS were analyzed. In comparison to the reference pre-scaler circuit, the proposed pre-scaler consumes 35.65% less power at 1GHz. CMOS 180nm technology in Cadence Virtuoso is used to realize circuits and Cadence Spectre is used to simulate circuits.

Keywords

• AVLS
• DMPS
• Flip-flop
• PTL
• TSPC