A low power and high speed decoder design based on FPGA

Abstract

In view of the complexity and inflexibility of the traditional encoding and decoding algorithms, this paper studies the forward propagation algorithm and structure of autoencoder neural networks. A low power consumption and high speed decoder system is proposed, using the autoencoder neural network as the codec algorithm with FPGA implementation. The system realizes the decoding of characters, and can be applied to the decoding of various multimedia information. Through ModelSim simulation and Xilinx ISE implementation, the hardware measurement are carried out, and the calculation accuracy, resource consumption, calculation speed and power consumption are analyzed. Experimental results show that the designed decoder can decode data correctly, the algorithm is efficient, scalable, the proposed system has the characteristics of low power consumption and high speed, and it can be widely used in a variety of low power, portable products.

Keywords

• FPGA
• decoder
• autoencoder neural network
• hardware implementation
• high speed and low power consumption