The Trusted UHF Receiver for Radio Frequency Identification of Critical Infrastructure Objects

Abstract

Results of designing the low-noise amplifier, quadrature demodulator, and baseband amplifier with an integrated low-pass filter for the UHF radio frequency identification receiver are presented. IP-blocks are designed for implementation in the domestic CMOS 180 nm technology process. The low-noise amplifier is implemented with integrated single pole double throw switches based on the MOSFETs which are needed for bypass mode realization at the RF input. The benefits of this approach are increased input linearity of the receiver by no less than 30 dB with an increase of a noise figure. The quadrature demodulator is realized according to a typical design based on the passive MOSFET mixer core. The programmable-gain baseband amplifier is implemented with an integrated low-pass filter based on Tow-Thomas biquad architecture. IP-blocks designed for use in an RFID reader transceiver VLSI IC with sensitivity value no more than -75 dBm and input linearity value not less than 10 dBm in a «Talk» mode. The trustiness of the receiver is provided by the full-cycle design procedure and verification under experimental investigation. The electric parameters values of the proposed receiver correspond to foreign VLSIs implemented in a CMOS process with the same technology nodes. Thus, it is important to design the domestic ISO 18000-6C reader equipment intended for critical infrastructure.

Keywords

• cmos, ip-block, receiver, uhf, tagging, radiofrequency identification.