An In-Memory-Computing Binary Neural Network Architecture With In-Memory Batch Normalization

Abstract

This paper describes an in-memory computing architecture that combines full-precision computation for the first and last layers of a neural network while employing binary weights and input activations for the intermediate layers. This unique approach presents an efficient and effective solution for optimizing neural-network computations, reducing complexity, and enhancing energy efficiency. Notably, multiple architecture-level optimization methods are developed to ensure the binary operations thereby eliminating the need for intricate “digital logic” components external to the memory units. One of the key contributions of this study is in-memory batch normalization, which is implemented to provide good accuracy for CIFAR10 classification applications. Despite the inherent challenges posed by the process variations, the proposed design demonstrated an accuracy of 78%. Furthermore, the SRAM layer in the architecture showed an energy efficiency of 1086 TOPS/W and throughput of 23 TOPS, all packed efficiently within an area of 60 TOPS/mm2. This novel in-memory computing architecture offers a promising solution for next-generation efficient and high-performance deep learning applications.

Keywords

• Batch normalization
• binary neural network
• edge device
• in-memory computing
• process variation
• SRAM