CAT-TWO: Counter-Based Adaptive Tree, Time Window Optimized for DRAM Row-Hammer Prevention

Abstract

Row-hammering flips bits in a victim DRAM row by frequently activating its adjacent rows, compromising DRAM integrity. Several studies propose to prevent row-hammering by counting the number of activates to a DRAM row and refreshing the corresponding victim rows before the count surpasses a row-hammer threshold. However, these approaches either incur a significant area overhead or a large number of additional activations (ACT) that could degrade the system performance. In this paper, we propose CAT-TWO, a time-window-optimized version of the existing Counter-based Adaptive Tree (CAT) scheme for row-hammer prevention. We first ensure that the victim rows are always refreshed at the last level of the tree without counter overflow by configuring the threshold and the number of CAT-TWO counters based on the fact that the maximum number of ACTs is limited within the refresh window. We further reduce the size and latency of CAT-TWO by applying high-radix rank-level CAT-TWO with multiple tree roots. CAT-TWO incurs less than 0.7% energy overhead on a baseline DDR4 DRAM device, and generates less than 0.03% additional ACTs to refresh victim rows in the worst case, which hardly affects system performance.

Keywords

• DRAM chips
• DRAM reliability
• row-hammering