Temperature influences of the interfacial layer in MOS (Pt/TiO2/Si) structures

Abstract

In this paper present I-V and C-V electrical characteristics of MOS (Pt/TiO2/Si) were reported. In the I-V characteristics the various electric parameter estimated such as the ideality factor (n), barrier height (FB), leakage current (Ic) and saturation current (Io) were estimated and further analyzed with Cheung functions. These electrical parameters were observed to be varying with heat treatment. The C-V characteristics, flat band voltage (VFB), interface trap density (Dit), effective charge density (Neff) and oxide trapped charge (Qot) were estimated and analyzed. The variation of these values with annealing temperature was correlated with restructuring and rearrangement of TiO2/SiO2 atoms at the metal/silicon interface. The hysteresis loop in counter clock wise voltage between -1 V to 1 V at 1 MHz frequency, after 600 °C heat treatment show the strong accumulation region, this may be due to the reduced interface trapped charge and dangling bond

Keywords

• leakage current
• ideality factor
• flat band voltage
• oxide trapped charge