A Robust Sparse RLS-Volterra Nonlinear Equalizer Using ℓ₀-Regularization for 4 × 150 Gbit/s IMDD-Based Optical Interconnect

Abstract

Volterra equalizer (VE) is a well-known and effective algorithm to deal with the linear and nonlinear distortions in optical interconnect, but the high computational complexity hinders its practical application. Generally, sparse VEs based on ℓ1- or ℓ0-regularization are good ways to reduce the complexity by discarding some inessential taps. However, a tap threshold needs to be chosen in these sparse VEs like the threshold-based pruned retraining VE (TR-VE) to decide the discarded taps. And this tap threshold should be adjusted fine to balance the reduced complexity and equalization performance, especially when the testing environments alter. Thus, the reduced complexity in these sparse VEs may fluctuate. To address this issue, a robust and stable complexity reduced sparse VE using ℓ0-regularization (ℓ0 -SR-VE) is proposed in this paper. The recursive least square (RLS) algorithm is used to replace the least mean square algorithm for the faster convergence speed and better equalization performance. The complexity of this equalizer depends on its parameters but not the tap threshold. Once the equalizer parameters are determined, the complexity would not change with the system characteristics, contributing to higher practicability. In our experiment, a 150 Gbit/s PAM8 signal transmission system based on intensity modulation and direct detection (IMDD) is achieved, and a dual-drive Mach-Zehnder modulator for optical single-sideband signal generation is used to mitigate the power fading effect. The experimental results show that with the help of ℓ0-SR-VE, the reduced complexity percentage is stable at 66.18% compared with the RLS-based VE, even after 75 km standard single-mode fiber (SSMF) transmission. By using this equalizer, 4×150 Gbit/s PAM8 signals have also been successfully transmitted over 30 km SSMF at C-band. The reduced complexity variation of ℓ0 -TR-VE is >20%, but the reduced complexity of the proposed ℓ0-SR-VE is stable at 60% even after 30 km SSMF for all four lanes.

Keywords

• PAM8
• IMDD system
• data center interconnect (DCI)
• sparse Volterra equalizer (VE)