Design and Enhancing Security Performance of Image Cryptography System Based on Fixed Point Chaotic Maps Stream Ciphers in FPGA

Abstract

Within this document, a novel system for image cryptography design utilizing fixed-point stream cipher chaotic maps is proposed. The system consists of fixed chaotic maps combined with generated 32-bit Pseudo Number (PN) all implemented using Field Programmable Gate Arrays (FPGA) through the Xilinx System Generator (XSG) environment. The most common chaotic maps-based cryptography involved in this work are Logistic, Lozi and Tent. The parameters of each type determine the key space required for decrypt the original pixel of plain image, Logistic map has one parameter r, Lozi has two parameters α and β, Tent has one parameter µ. The main idea was to combine another parameter pseudo number (PN) to increase key space, which is the main measure of security performance against brute force attack. An innovative pseudorandom bit generator (PRBG) referred to as XORing these chaotic maps were called the fixed-point cascade chaotic maps-PRBG (FPCCM-PRBG), with an eight least significant bits of 32-bit pseudo number generator (PN) this method is known as fixed point cascade chaotic maps-PNBG (FPCCM-PRNBG). The randomness of the generated keys was evaluated using the National Institute of Standards and Technology (NIST) tests, including frequency, Frequency (Mono bit) and runs test. The security performance assessed through histogram analysis, correlation coefficient analysis, information entropy, pixel changing rate, and structural similarity. Xilinx system generator is an effective tool embedded in MATLAB/SIMULINK environment utilized for the work implementation. The system implemented using co-simulation method on the ZYNQ 7000 SoC ZC702 Evaluation Kit, with a key space of 2288 and a throughput of 269. 32 MB/sec.

Keywords

• Chaotic maps, FPGA, Image cryptography, Pseudo number, Security, Xilinx system generator.