An improvement of both security and reliability for AES implementations

Abstract

Cryptographic circuits, because they contain confidential information, are subject to fraudulent manipulations, commonly called attacks, by ill-intentioned people. Several attacks have been identified and analyzed. One of the most efficient attacks, called DFA (Differential Fault Analysis) cryptanalysis, exploits the presence of faults, injected voluntarily by the attacker, for example with a laser, in the calculations. Countermeasures are then developed and validated to protect the hardware implementation of cryptographic algorithms such as AES algorithm. The present paper aims to protect the AES algorithm against fault injection attacks. In this paper, an efficient fault detection method for the AES algorithm has been developed. In our proposed design, the AES round architecture is devised into three parts and two pipelines registers are inserted in between. Our simulations show that fault detection capabilities of the proposed method for random fault archives 99.539%. The error detection structure can detect the inserted faults with good coverage using the proposed approach. In order to verify the accuracy of our results, we compare our implementation result with the results presented in the literature. Note that the results obtained are competitive with existing implementations. Our fault detection method has the ability to achieve a compromise of safety level and low implementation cost.

Keywords

• AES algorithm
• Information Security
• Hardware implementation
• Fault Attacks
• Countermeasures
• FPGA (Field Programmable Gate Arrays)