DESIGN AND SIMULATION OF A HIGH PERFORMANCE CMOS VOLTAGE DOUBLERS USING CHARGE REUSE TECHNIQUE

Abstract

Voltage doubler (VD) structure plays an important role in charge pump (CP) circuits. It provides a voltages that is higher than the voltage of the power supply or a voltage of reverse polarity. In many applications such as the power IC and switched-capacitor transformers. This paper presents the design and analysis for VD using charge reuse technique CMOS 0.35µm tech. with high performance. Bootstrapped and charge reuse techniques is used to improve performance of integrated VD. Charge reusing method is based on equalizing the voltages of the pumping capacitances in each stage of CP. As a consequence, it reduces the load independent losses, improve the efficiency. Simulation using Orcad is applied for various VD structures shows improvement in charge reuse technique compared with existing counterpart. The results obtained show that the VD can be used in a wide band frequencies (0-100 MHz) or greater. The charge reuse VD circuit provided a good efficiency about (87.6%) and (83.5%) for one stage and two stage respectively at pump capacitance of 57pf, load current of 1mA, frequency of 10 MHz and supply voltage is 3.5 V compared with one stage and two stage of a latched VD are (85.4%) and (80%) respectively.

Keywords

• Latched VD
• Charge reuse VD
• Pump capacitance
• Power losses