A generation and distribution system of clock signal source for signal acquisition system

Abstract

Abstract The clock signal is the heartbeat of modern electronic system, and demands of increasing high‐quality signal has been raised, with the development of science and technology in the field of electronic information. The clock signal with low jitter is helpful to improve the signal‐to‐noise ratio (SNR) of sampled data and obtain high‐precision result. In this article, a programmable clock system of signal generation and distribution is designed for high‐speed acquisition system. The system can provide the clock of low jitter which frequency is as high as 3.2 GHz. The output channels for clock are 14 and each channel for clock can also be configured for synchronizing, delay adjusting or calibrating. Based on the system, a new type of configuration program is developed by using Verilog language. It can directly control the chip which has better compatibility in the application scenario of Field Programmable Gate Array (FPGA) as the master chip. It also provides a reference and guidance for the design and implementation of the dual‐Phase Locked Loop clock chips. When it provides the clocks for the high‐speed acquisition system, the SNR of the acquisition signal has been significantly improved compared with similar acquisition systems. It indicates that the clock system we designed provides an effective way for the high‐speed acquisition system to obtain the data with higher SNR.

Keywords

• ADC
• clock system
• high‐speed acquisition
• low jitter
• SNR
• synchronous