Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes

Abstract

In this paper, the Reed Solomon Code is decoded using the Welch-Berlekamp Algorithm. The RS Decoder is implemented using Hardware Description Language VHDL (VHSIC hardware Description Language) and simulated on Modelsim software. Some modifications have been carried out on the Welch Berlekamp algorithm in such a way that it is easier to implement. A pilot design double error correction RS(63, 59) decoder has been written in VHDL and simulated. The XILINX FPGA layout RS(63, 59) is then obtained.

Keywords

• FPGA
• Hard decision decoding
• Reed Solomon Code
• Welch Berlekamp algorithm